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-- Company: 
-- Engineer: 
-- 
-- Create Date:    19:40:59 04/03/2008 
-- Design Name: 
-- Module Name:    STAGE_WB - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY STAGE_WB IS
  PORT (MEMWB_IR     : IN  std_logic_vector(31 DOWNTO 0);
        MEMWB_ALUOUT : IN  std_logic_vector(15 DOWNTO 0);
        MEMWB_LMD    : IN  std_logic_vector(15 DOWNTO 0);
        WB_C         : OUT std_logic_vector(15 DOWNTO 0);
        WB_IND       : OUT std_logic_vector(4 DOWNTO 0);
        WB_WE        : OUT std_logic);
END STAGE_WB;

ARCHITECTURE Behavioral OF STAGE_WB IS

BEGIN
  -- Setup combinatorial WB stage (this will connect to the ID stage where the
  -- register file is held, thus if this was registered it would take an extra
  -- CT)
  PROCESS (MEMWB_IR, MEMWB_ALUOUT, MEMWB_LMD) IS
  BEGIN  -- PROCESS
    IF MEMWB_IR /= (31 DOWNTO 0 => '0') THEN
      CASE MEMWB_IR(28 DOWNTO 26) IS
        WHEN "000" =>                   -- ALU
          WB_IND <= MEMWB_IR(15 DOWNTO 11);
          WB_C   <= MEMWB_ALUOUT;
          WB_WE  <= '1';
        WHEN "001" =>                   -- Load
          WB_IND <= MEMWB_IR(20 DOWNTO 16);
          WB_C   <= MEMWB_LMD;
          WB_WE  <= '1';
        WHEN "110" =>                   -- LI
          WB_IND <= MEMWB_IR(25 DOWNTO 21);
          WB_C   <= MEMWB_ALUOUT;
          WB_WE  <= '1';
        WHEN OTHERS =>
          WB_IND <= (OTHERS => '0');
          WB_C   <= (OTHERS => '0');
          WB_WE  <= '0';
      END CASE;
    ELSE
      WB_IND <= (OTHERS => '0');
      WB_C   <= (OTHERS => '0');
      WB_WE  <= '0';
    END IF;
  END PROCESS;
END Behavioral;
